As electronics products become more complex, demands placed upon microelectronic device packaging increase. For example, mobile electronics products such as cellular phones continue to decrease in size and cost while providing higher levels of functionality. As a result, microelectronic devices such as semiconductor chips for electronic products often require numerous input and output connections to other electronic components. To meet these demands, microelectronic devices are increasingly packaged in chip-scale and multi-chip packages to facilitate device testing and connection to other electronic components of the electronic products.
Terminals for microelectronic devices are typically disposed in regular grid-like patterns, substantially covering the bottom surface of the device (commonly referred to as an “area array”) or in elongated rows extending parallel to and adjacent each edge of the device's front surface. Accordingly, packages for such a microelectronic devices may employ a connection structure having prefabricated arrays or rows of leads/discrete wires, solder bumps or combinations of both for connection with the device. Techniques for making the interconnections between the microelectronic device and the package include, for example, wire bonding, tape automated bonding (“TAB”) and flip/chip bonding.
The flip-chip bonding configuration yields a particularly compact assembly. In this configuration, the front or contact-bearing surface of the microelectronic device faces towards a connection structure. Each contact on the device is joined by a solder bond to a corresponding contact pad on the connection structure, by positioning solder balls on the connection structure or device, juxtaposing the device with the connection structure in the front-face-down orientation, and momentarily reflowing the solder. As a result, the assembly occupies an area of the connection structure no larger than the area of the chip itself.
As the number of interconnections per microelectronic device increases and the size of microelectronic devices decrease, the number of contacts per unit area of the front surface also increases. Accordingly, the contact pitch for the device becomes finer. Since many packaging configurations require a contact pitch that corresponds to the pitch of the device contacts, there is a need for connection structures having an increasingly finer contact pitch or greater contact density. In particular, such connection structures are well suited for the flip-chip bonding configurations.
A number of approaches have been proposed for the production of packaging having contacts of a fine pitch. Such approaches may involve the production of a plurality of posts extending from a surface of a substrate. For example, metallic posts may be produced on a metallic substrate surface through the use of stamping techniques known in the art.
Chemical techniques may be used as well. For example, U.S. Pat. No. 6,177,636 to Fjelstad describes a connection component that includes a substrate and a plurality of substantially rigid, elongated posts protruding parallel to one another from a substrate surface. The connection component may be formed by attaching a substrate to a conductive sheet and is then selectively removing portions of the conductive sheet, e.g., using an etching process, to produce a plurality of posts each extending from a base at the substrate to a tip. The tips may have coplanar surfaces. Once the tips are electrically connected to contacts of a microelectronic device, the posts become individual interconnections between the microelectronic device and the substrate.
Similarly, U.S. Pat. Nos. 6,528,874 and 6,646,337, each to Iijima et al., also describe methods for substrates for mounting electronic devices, such as integrated circuits (ICs) and large-scale integrated circuits (LSI circuits). The wiring substrates are formed by selectively etching a copper foil laminate so as to form layers having posts of uniform height. The layers may be stacked to form wiring circuit layers. Improved reliability of electrical connections is attributed to the uniformity in post height.
In addition, electrolytic plating methods for forming posts on a metal substrate are described in U.S. Pat. Nos. 6,372,620 and 6,617,236, each to Oosawa et al. These methods are similar to the methods described in U.S. Pat. Nos. 6,528,874 and 6,646,337 in that they each employ masking technologies to control the locations of post formation. Unlike etching processes in which exposed portions of a conductive layer on a substrate are removed, posts are formed by depositing metal on the exposed portions of the substrate.
Nevertheless, there exists further opportunities in the art to provide connection structures having increasingly finer contact pitch and/or greater contact density.